Architecture Question:

Latches are Level Sensitive, while Flip-Flops are Edge Sensitive. A positive level latch is transparent to the positive level (enable), and it lathes the final input before it is changing its level (i.e. before enable goes to '0' or before the clock goes to -ve level.

A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negedge flop) only.