RAM Interview Preparation Guide

Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the chip to work on several memory access commands at a time, interleaved among the separate banks. This allows higher data access rates than an asynchronous DRAM.

Direct Rambus DRAM or DRDRAM (sometimes just called Rambus DRAM or RDRAM) is a type of synchronous dynamic RAM. RDRAM was developed by Rambus inc., in the mid-1990s as a replacement for then-prevalent DIMM SDRAM memory architecture.

RDRAM was initially expected to become the standard in PC memory, especially after Intel agreed to license the Rambus technology for use with its future chipsets. Further, RDRAM was expected to become a standard for VRAM. However, RDRAM got embroiled in a standards war with an alternative technology - DDR SDRAM, quickly losing out on grounds of price, and, later on, performance. By the early 2000s, RDRAM was no longer supported by any mainstream computing architecture.

Ferroelectric RAM is a random-access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile random-access memory technologies that offer the same functionality as flash memory. FeRAM advantages over flash include: lower power usage, faster write performance and a much greater maximum number of write-erase cycles. Disadvantages of FeRAM are much lower storage densities than flash devices, storage capacity limitations, and higher cost.

Error-correcting code memory (ECC memory) is a type of computer data storage that can detect and correct the more common kinds of internal data corruption. ECC memory is used in most computers where data corruption cannot be tolerated under any circumstances, such as for scientific or financial computing.

ECC memory maintains a memory system effectively free from single-bit errors: the data that is read from each word is always the same as the data that had been written to it, even if a single bit actually stored, or more in some cases, has been flipped to the wrong state. Some non-ECC memory with parity support allows errors to be detected, but not corrected; otherwise errors that may occur are not detected.

tRCD is the number of clock cycles delay required between an active command row address strobe (RAS) and a CAS. It is the time required between the memory controller asserting a row address, and then asserting a column address during the subsequent read or write command. tRCD stands for row address to column address delay time.

tCAS is the number of clock cycles needed to access a certain column of data in SDRAM. CAS latency is the column address strobe time, sometimes referred to as tCL.

tRP is the number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. It stands for row precharge time.

tRAS is the minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin.com, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out. [1]. It stands for row address strobe time.

Shadow RAM is a copy of Basic Input/Output Operating System (BIOS) routines from read-only memory (ROM) into a special area of random access memory (RAM) so that they can be accessed more quickly. Access in shadow RAM is typically in the 60-100 nanosecond range whereas ROM access is in the 125-250 ns range. In some operating systems such as DOS, certain BIOS routines are not only used during the boot or startup of the system, but also during normal operation, especially to drive the video display terminal. In Windows and OS/2, however, these routines are not used and the use of shadow RAM is not necessary. In some systems, the user can turn the use of shadow RAM off or on.

RAM parity checking is the storing of a redundant parity bit representing the parity odd or even of a small amount of computer data typically one byte stored in random access memory, and the subsequent comparison of the stored and the computed parity to detect whether a data error has occurred.

The parity bit was originally stored in additional individual memory chips; with the introduction of plug-in DIMM, SIMM, etc. modules, they became available in non-parity and parity (with an extra bit per byte, storing 9 bits for every 8 bits of actual data) versions.