Architecture Interview Preparation Guide

Pipeline is a process where a business object goes through several stages asynchronously, where one stage picks up processes and drops it for the next process to pick up. The hazard is when the different thread of the same process picks up the business object leads to malfunction. This can be handled by status handling or scan delays.

Memory Management is a crucial role in every operating system. Memory management is there are many types such as

1. Storage memory Management

2. I/O Memory Management

Caching is often considered as a performance-enhancement tool than a way to store application data. If u spends more server resources in accessing the same data repeatedly, use caching instead. Caching data can bring huge performance benefits ,so whenever u find that u need to frequently access data that doesn’t often change, cache it in the cache object and your application's performance will improve.

Race conditions are a severe way crashing the server/ system at times. Generally, this problem arises in priority less systems or the users who have equal priority will be put to this problem. Race condition is a situation in which a resource D is to be serviced to a process A and the process B that holds the resource C is to be given to the process A. So a cyclic chain occurs and no way the resources will be get shared and also the systems with equal priority wont get the resource so that the system wont come out of the blocked state due to race condition!

Latches are Level Sensitive, while Flip-Flops are Edge Sensitive. A positive level latch is transparent to the positive level (enable), and it lathes the final input before it is changing its level (i.e. before enable goes to '0' or before the clock goes to -ve level.

A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negedge flop) only.

When considering the reconstruction of a signal, we are familiar with the idea of the Nyquist rate. This concept allows us to find the sampling rate that will provide for perfect reconstruction of our signal. If we sample at too low of a rate (below the Nyquist rate), then problems will arise that will make perfect reconstruction impossible - this problem is known as aliasing. Aliasing occurs when there is an overlap in the shifted, periodic copies of our original signal's FT, i.e. spectrum.

Bus contention occurs when more than one memory module attempts to access the bus simultaneously. It can be reduced by using hierarchical bus architecture.

Caching can be done with so many ways like page caching, output caching etc. With ASP.NET, we can achieve this efficiently and by using CLR, which shows a direct impact on the Caching feature in .NET technology.

Each place in cache records block's tag (as well as its data) Of course, place in cache may be unoccupied, so usually place maintains valid bit so to find block in cache:

Use index of block address to determine place (or set of places)

For that (or each) place, check valid bit is set and compare tag with that of block address --- this can be done in parallel for all places in a set.

There are two types of pipelines-

Instructional pipeline where different stages of an instruction fetch and execution are handled in a pipeline.

Arithmetic pipeline are different stages of an arithmetic operation are handled along the stages of a pipeline.