Electronics Engineering Question:

When the input to the JK flip-flop is j=1 and k=1, the race around condition occurs, i.e it occurs when the time period of the clock pulse is greater than the propagation delay of the flip flop. so the output changes or toggles in a single clock period. If it toggles even number of times the output is same but if it toggles odd number of times then the output is complimented. To avoid race around condition we cant make the clock pulse smaller than the propagation delay so we use
1. Master slave JK flip flop
2. Positive or negative edge triggering
Since the hardware cost of msjk is more edge triggering is preferred to msjk.