86 Family Question: Download 86 Family PDF
Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal?
Answer:
Put even number of not gates between clocks of reg A and
Reg B. The not gates will introduce delay between clock of
reg A and reg B.
Reg B. The not gates will introduce delay between clock of
reg A and reg B.
Previous Question | Next Question |
Design a divide-by-3 sequential circuit with 50% duty circle now? | What are different Adder circuits you studied? |