VLSI Question:

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Is a widely used cache coherency and memory coherence
protocol introduced by Intel. Modified Exclusive Shared
Invalid are the protocol States.

M means value has been modified from main memory and the
cache is required to write the data back to main memory,
before permitting any other read of the main memory state.
(ITS DIRTY)

E IS CLEAN: Value Match with main memory

S Cache may be stored in other caches of the machine

I Invalid